In using digital storage means (e.g., flip-flops), workers are at times confronted with "multiple" clock signals; i.e., signals generated or received with respect to two or more different clock sources.
These multiple clocks are often derived from different oscillator circuits and therefore are asynchronous. This means that there is no relationship between the frequency or the phase of these clocks.
In designing logic circuits which contain signals generated by two or more asynchronous clocks, the designer must be careful to avoid metastability problems. A flip-flop is said to become metastable when its input changes at same time as the clock signal that is clocking-in the input data such that the flip-flop output value takes an unusually long time to settle to a stable value.
To avoid "metastability" problems, one can use synchronizing circuits which take, as input, signals generated with respect to one clock, and as output, a version of the incoming signal that is synchronized to a second clock signal which was asynchronous to the first clock. Although the possibility of metastability still exists in these circuits, it can be localized to small block of logic; and, its probability of causing malfunctions in the rest of the design is rather insignificant.
One possible method of synchronizing is to use two flip flops in series; e.g., note FIG 1: a pair of "D type" flip-flops, assumed to be "edge-triggered", --- , with output clocked from a common source (Note: another"edge-trigger" means can be substituted.
In this configuration, a change in the input signal appears on the output a maximum of two clock periods after it appears at the input to the first flip-flop. In this situation, the first flip-flop still may become metastable if the data changes at the rising edge of the clock, but as long as this metastability resolves within one clock period, the output of the second flip-flop will always be valid and will output a signal synchronized to the clock signal. This can be referred to as "level synchronization" because the synchronized output eventually reflects the level of the input, whether it is high or low. Such synchronization carries the restriction that, after changing value, the input signal must remain at the new value longer than the period of the synchronizing clock (pulse persistence)--whereby to assure that the output will eventually reflect the new value.
Occasionally, a designer may want to synchronize a signal which represents some event, such as loading a register, clearing a counter, or detecting an error. Such an event is commonly represented by a short pulse which is exactly one clock period in length. If the clock to which this signal is to be synchronized is slower than the clock which was used to generate the pulse, then this signal will not meet the "level synchronizer's" restriction that the input remain stable for longer than the period of the synchronizing clock. In this situation another form of synchronizer is required.
We have developed "pulse synchronizers" designed to handle just such situations. Two such synchronizers are described here; each has different characteristics and restrictions on the types of pulses it will synchronize.
It is an object hereof to address such needs, and provide related features. A related object is to teach "pulse synchronizer" means, e.g., to address metastability
logic circuit involves multiple asynchronous where a clocks.
Other objects and advantages of the present invention will be apparent to those skilled in the art.